1. Field of the Invention
This invention relates to an apparatus for reading signals out of a solid-state image sensing device such as a CCD (charge-coupled device).
2. Description of the Related Art
FIG. 25 illustrates an example of a conventional apparatus for reading signals out of a CCD, and FIG. 26 is a waveform diagram of signals which flow into each circuit of the apparatus shown in FIG. 25.
The CCD 10 includes a number of photodiodes 2 arrayed in the vertical and horizontal directions. By irradiating the CCD 10 with light, signal charge conforming to the amount of irradiation is accumulated in the photodiodes 2. By applying driving pulses to the CCD 10, the signal charge that has accumulated in the photodiodes 2 is applied to a floating diffusion amplifier circuit (FDA) 5 via vertical transfer lines 3 and a horizontal transfer line 4. The signal charge is amplified in the FDA 5 and then outputted from the CCD 10, in the manner described below, as a video signal component S.sub.3.
Whenever the signal charge that has accumulated in one photodiode is read out (the period at which this occurs is referred to as one pixel period T), a reset pulse is applied to the FDA 5, whereby the FDA 5 is reset, as shown in FIG. 26. By adding the reset pulse component to the output signal of the horizontal transfer line 4 during the time period t.sub.1 that the H-level reset pulse is being applied to the FDA 5, a first signal component S.sub.1 having a predetermined level is outputted from the CCD 10. When the reset pulse reverts from the H level to the L level, a feed-through signal component S.sub.2 having a level lower than that of the first signal component S.sub.1 is outputted from the CCD 10 during a feed-through time period t.sub.2. When the feed-through time period t.sub.2 elapses, a video signal component S.sub.3 having a level which corresponds to the amount of signal charge that has accumulated in the photodiodes 2 is outputted during a video signal time period t.sub.3. The level of the feed-through signal component S.sub.2 is used as the reference level of the video signal component S.sub.3.
The first signal component S.sub.1 contains noise to some extent. Consequently, the level of the feed-through signal component S.sub.2 fluctuates owing to noise contained in the first signal component S.sub.1 at the moment t of the transition from the reset time period t.sub.1 to the feed-through time period t.sub.2. For example, if the noise spikes at the transition point t, as indicated at A in FIG. 26, the level of the feed-through signal component S.sub.2 rises correspondingly. Conversely, if the noise declines at the transition point t, as indicated at B, the level of the feed-through signal component S.sub.2 also falls. This fluctuation in the level of the feed-through signal component S.sub.2, which fluctuates as a result of the noise in the first signal component S.sub.1, is referred to as "reset noise." The video signal component S.sub.3 also is influenced by the noise contained in the first signal component S.sub.1 and the level thereof fluctuates in the same manner as the level of the feed-through signal component S.sub.2. The difference between the levels of the feed-through signal component S.sub.2 and video signal component S.sub.3 represents the amount of signal charge that has accumulated in the photodiodes 2 of the CCD 10, irrespective of whether reset noise is present or not.
A correlated double-sampling (referred to as "CDS" below) circuit is known as a CCD output-signal readout circuit which detects a signal representing the difference in levels mentioned above. The CDS circuit extracts the feed-through signal component S.sub.2 and video signal component S.sub.3 by sampling the CCD output signal in the feed-through time period t.sub.2 and in the video signal time period t.sub.3, and eliminates the reset noise component by taking the difference between these extracts signal components.
However, the signal outputted by the CCD 10 includes not only reset noise but also a high-frequency noise component for which there is no correlation between the feed-through time period t.sub.2 and video signal time period t.sub.3. Such high-frequency noise causes a deterioration in the S/N ratio because it is reflected in the low-frequency region owing to the sampling operation of the CDS circuit.
An integrating-type correlated double-sampling circuit of the kind shown in FIG. 25 is known as a circuit capable of eliminating the drawbacks of the CDS circuit described above. In the apparatus illustrated in FIG. 25, integrating circuits 111, 112 are provided in front of a CDS circuit 117 composed of sample-and-hold circuits 113, 114, 115 and a differential amplifier circuit 116. The output signal of the CCD 10 is applied to the integrating circuits 111, 112 via a buffer circuit 11. The integrating circuit 112 comprises a resistor 121, a gate switch 122, a capacitor 123, a reset switch 124 and a buffer amplifier circuit 125. A gate pulse PG.sub.A1 is applied to the gate switch 122 in such a manner that the output signal of the CCD will be integrated during the feed-through time period t.sub.2. A reset pulse RS.sub.A1 for resetting the integrating capacitor 123 is applied to the reset switch 124 immediately before this integration starts. Similarly, the integrating circuit 111 comprises a resistor 126, a gate switch 127, a capacitor 128, a reset switch 129 and a buffer amplifier circuit 130. A gate pulse PG.sub.B1 is applied to the gate switch 127 in such a manner that the output signal of the CCD will be integrated during the video signal period t.sub.3. A reset pulse RS.sub.B1 for resetting the integrating capacitor 128 is applied to the reset switch 129. Thus, integrated signals corresponding to the feed-through signal component S.sub.2 and video signal component S.sub.3 are obtained from the outputs of the integrating circuits 112, 111, respectively. These integrated outputs are sampled and held and then fed into the differential amplifier circuit 116, whence a video signal from which reset noise has been canceled is obtained. Since high-frequency noise components contained in the CCD output signal are eliminated by the integrating circuits in this integrating-type CDS circuit, the reflecting of these high-frequency noise components in the low-frequency region owing to the sampling operation is reduced and it is possible to achieve CCD signal readout in which the effect of noise reduction is outstanding.
With a CCD signal readout apparatus of this kind, however, the charging and discharging currents in the integrating circuits become extremely small when the output signal level of the CCD is small, the linearity of integration diminishes and the apparatus is readily susceptible to noise from other circuits.
FIG. 27 illustrates another example of a conventional apparatus for reading signals out of a CCD, and FIG. 28 is a waveform diagram of signals which flow into the various circuits of the apparatus shown in FIG. 27. Items in FIGS. 27 and 28 that are identical with those shown in FIGS. 25 and 26 are designated by like reference characters and need not be described again.
In order to detect the signal representing the difference in the levels between the feed-through signal component S2 and video signal component S3, the apparatus shown in FIG. 27 is provided with an inverting amplifier circuit 131, a non-inverting amplifier circuit 132 and gate circuits 133A and 133B. A signal outputted by the CCD 10 is applied to the inverting amplifier circuit 131 and the non-inverting amplifier circuit 132. A signal inverted and amplified by the inverting amplifier 131 is applied to the first gate circuit 133A. A signal amplified by the non-inverting amplifier circuit 132 is applied to the second gate circuit 133B. A first gate pulse PG.sub.A2 which attains the H level during the time of the feed-through time period t.sub.2 is applied to the first gate circuit 133A, and a second gate pulse PG.sub.B2 which attains the H level during the time of the video signal time period t.sub.3 is applied to the second gate circuit 133B. When the applied gate pulses PG.sub.A2 and PG.sub.B2 at the H level, the input signals pass through the gate circuits 133A and 133B, whereby the feed-through signal component S.sub.2 and video signal component S.sub.3 are obtained. By adding the signals that have passed the through gate circuits 133A and 133B, a signal representing the level difference between the feed-through signal component S.sub.2 and video signal component S.sub.3 is obtained. This difference signal represents video.
The signal outputted by the CCD 10 contains not only reset noise but also noise, such as high-frequency noise, in which there is no correlation between the feed-through time period t.sub.2 and video signal time period t.sub.3. As before, such noise is included in the signal representing the level difference between the feed-through signal component S.sub.2 and video signal component S.sub.3. In order to reduce this noise, the apparatus shown in FIG. 27 is provided with an integrating circuit 134 for integrating the difference signal. The noise is reduced by using the integrating circuit 134 to integrate the signals representing the level difference.
To detect a difference in integrated values correctly, it is required that the integrating interval in the feed-through signal time period and the integrating interval in the video signal time period be made to coincide. This means that the integrating interval must be made to conform to the shorter of the feed-through signal time period and video signal time period. Consequently, efficacious integration cannot be carried out over a long integration time.